Verilog
1 language| Type | Interactive demo |
|---|---|
| Origin | ECE 111 at UC San Diego |
| Developer | David |
| Written in | SystemVerilog, Icarus Verilog, TypeScript, Canvas |
| Tests | Icarus Verilog benches plus a TypeScript model checked cycle by cycle against the RTL |
| Built with | ECE 111 coursework ported into a browser demo |
| Hosted on | David-Internet/demos/verilog |
| Website | https://david-internet.vercel.app/demos/verilog |
Verilog is an interactive demonstration of an eight-state Viterbi decoder and an RTL module library based on ECE 111 work at UC San Diego. It presents a convolutional encoder, noisy channel, animated trellis, and traceback in the browser.[1]
The page also includes live versions of course modules such as UART transmitters and receivers, a barrel shifter, LFSR, carry-lookahead adder, counters, and an ALU. Its waveforms come from build-time Icarus Verilog simulations.
Overview
Visitors can enter a message, select an error pattern, and observe the encoded and decoded bits. A logic-analyzer panel shows per-cycle path metrics and output traces, while the module shelf pairs each widget with RTL and testbench results.
Viterbi decoder
The rate-1/2 decoder uses eight states, branch-metric blocks, survivor registers, and traceback logic. In the trellis, eight add-compare-select units race down the trellis as the decoder selects survivor paths and recovers the message.
Development
The demo ports ECE 111 coursework to TypeScript and Canvas. The TypeScript model is checked cycle by cycle against the RTL, and Icarus Verilog testbenches provide pass or fail results for channel patterns and module implementations. Icarus Verilog benches plus a TypeScript model checked cycle by cycle against the RTL.
See also
References
- ^
content/verilog/README.md, David's Internet.
- Interactive demos
- Digital design
- 2026 establishments